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quad, 10-bit nano dac with 2 ppm/c reference, i 2 c interface data sheet AD5316R rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features low drift 2.5 v on-chip reference: 2 ppm/c typical tiny package: 3 mm 3 mm, 16-lead lfcsp total unadjusted error (tue): 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum high drive capability: 20 ma, 0.5 v from supply rails user-selectable gain of 1 or 2 (gain pin) reset to zero scale or midscale (rstsel pin) 1.8 v logic compatibility 400 khz i 2 c-compatible serial interface 4 i 2 c addresses available low glitch: 0.5 nv-sec robust 3.5 kv hbm and 1.5 kv ficdm esd rating low power: 3.3 mw at 3 v 2.7 v to 5.5 v power supply ?40c to +105c temperature range applications digital gain and offset adjustment programmable attenuators industrial automation data acquisition systems functional block diagram figure 1. general description the AD5316R , a member of the nano dac? family, is a low power, quad, 10-bit buffered voltage output dac. the device includes a 2.5 v, 2 ppm/c internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 v (gain = 1) or 5 v (gain = 2). the device operates from a single 2.7 v to 5.5 v supply, is guaranteed monotonic by design, and exhibits less than 0.1% fsr gain error and 1.5 mv offset error performance. the device is available in a 3 mm 3 mm lfcsp package and in a tssop package. the AD5316R also incorporates a power-on reset circuit and a rstsel pin; the rstsel pin ensures that the dac outputs power up to zero scale or midscale and remain at that level until a valid write takes place. the part contains a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 a at 3 v. the AD5316R uses a versatile 2-wire serial interface that operates at clock rates up to 400 khz and includes a v logic pin intended for 1.8 v/3 v/5 v logic. table 1. related devices interface reference 12-bit 10-bit spi internal ad5684r ad5317r external ad5684 ad5317 i 2 c internal ad5694r external ad5694 ad5316 1 1 the AD5316R and the ad5316 are not pin-to-pin or software compatible. product highlights 1. precision dc performance. total unadjusted error: 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum 2. low drift 2.5 v on-chip reference. 2 ppm/c typical temperature coefficient 5 ppm/c maximum temperature coefficient 3. two package options. 3 mm 3 mm, 16-lead lfcsp 16-lead tssop scl v logic sda a1 a0 input register dac register string dac a buffer v out a input register dac register string dac b buffer v out b input register dac register string dac c buffer v out c input register dac register string dac d buffer v out d v ref gnd v dd 2.5v reference power- down logic power-on reset gain = 1/2 interface logic rstsel gain ldac reset AD5316R 10819-001
AD5316R data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteris tics ........................................................................ 4 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 ter mi nolo g y .................................................................................... 14 theory of operation ...................................................................... 16 digital - to - analog conver ter .................................................... 16 transfer function ....................................................................... 16 dac architecture ....................................................................... 16 serial inter face ............................................................................ 17 write and update commands .................................................. 17 i 2 c slave address ........................................................................ 18 serial operation ......................................................................... 18 write operation .......................................................................... 18 read operation ........................................................................... 19 multiple dac readback sequence .......................................... 19 power - down operation ............................................................ 20 load dac (hardware ldac pin) ........................................... 20 ldac mask register ................................................................. 21 hardware reset pin ( reset ) ................................................... 21 reset select pin (rstsel) ........................................................ 21 internal reference setup ........................................................... 22 solder heat reflow ..................................................................... 22 long - term temperature drift ................................................. 22 thermal hysteresis .................................................................... 22 applications information .............................................................. 23 microprocessor interfacing ....................................................... 23 AD5316R to adsp - bf531 interface ....................................... 23 layout guidelines ....................................................................... 23 galvanically isolated interface ................................................. 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision histor y 7/ 12 rev. 0 to rev. a change to features section ............................................................. 1 change to relative accuracy parameter in table 2 ..................... 3 change to differential nonlinearity parameter in table 2 ......... 3 changes to ordering guide .......................................................... 24 7 /12 revision 0: initial version
data sheet AD5316R rev. a | page 3 of 24 specifications v dd = 2.7 v to 5.5 v; v ref = 2. 5 v; 1.8 v v logic 5.5 v; r l = 2 k?; c l = 200 pf ; a ll specifications t min to t max , unless otherwise noted . table 2. parameter min typ max unit test conditions/comments 1 , 2 static performance 3 resolution 10 bits relative accuracy 0.12 0. 5 lsb differential nonlinearity 0. 5 lsb guaranteed monotonic by design zero - code error 0.4 1.5 mv all 0s loaded to dac register offset error +0.1 1.5 mv full - scale error +0.01 0.1 % of fsr all 1s loaded to dac register gain error 0.02 0.1 % of fsr total unadjusted error 0.01 0.1 % of fsr external reference , gain = 2 , tssop 0.2 % of fsr internal reference , gain = 1 , tssop offset error drift 4 1 v/c gain temperature coefficient 4 1 ppm of fsr/c dc power supply rejection ratio 4 0.15 mv/v dac code = midscale; v dd = 5 v 10% dc crosstalk 4 2 v due to single channel, full - scale output change 3 v/ma due to load current change 2 v due to power - down (per channel) output characteristics 4 output voltage range 0 v ref v gain = 1 0 2 v ref v gain = 2 ( see figure 26) capacitive load stability 2 nf r l = 10 nf r l = 1 k resistive load 5 1 k load regulation dac code = midscale 80 v/ma 5 v 10%; ?30 ma i out +30 ma 80 v/ma 3 v 10% ; ?20 ma i out + 20 ma short - circuit current 6 40 ma load impedance at rails 7 25 see figure 26 power - up time 2.5 s coming out of power - down mode; v dd = 5 v reference output output voltage 8 2.4975 2.5025 v at t a reference tc 9 2 5 ppm/c see the terminology section output impedance 4 0.04 output voltage noise 4 12 v p -p 0.1 hz to 10 hz output voltage noise density 4 240 nv/hz at t a , f = 10 khz, c l = 10 nf load regulation , sourcing 4 20 v/ma at t a load regulation , sinking 4 40 v/ma at t a output current load capability 4 5 ma v dd 3 v line regulation 4 100 v/v at t a long - term stability/drift 4 12 ppm after 1000 hours at 125c thermal hysteresis 4 125 ppm first cycle 25 ppm additional cycles logic inputs 4 input current 2 a per pin input low voltage , v inl 0.3 v logic v input high voltage , v inh 0.7 v logic v pin capacitance 2 pf
AD5316R data sheet rev. a | page 4 of 24 parameter min typ max unit test conditions/comments 1 , 2 logic outputs (sda) 4 output low voltage, v ol 0.4 v i sink = 3 ma floating state output capacitance 4 pf power requirements v logic 1.8 5.5 v i logic 3 a v dd 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 10 0.59 0.7 ma internal reference off 1.1 1.3 ma internal reference on, at full scale all power - down modes 11 1 4 a ?40c to +85c 6 a ?40c to +105c 1 temperature range is ?40c to + 105c . 2 the AD5316R and the ad5316 are not pin - to - pin or software compatible. 3 dc specifications are tested with the outputs unloaded, unless otherwise noted. upper dead band (10 mv) exists only when v ref = v dd with gain = 1 or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 4 to 1020. 4 guaranteed by design and characterization; not production tested. 5 channel a and channel b can have a combined output current of up to 30 ma. similarly, channel c and channel d can have a combined output current of up to 30 ma up to a junction temperature of 110c. 6 v dd = 5 v . the device includes current limiting that is intended to protect the device during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the specified max imum junction temperature may impair device reliability. 7 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 typical chan nel res istance of the output devices. for example , when sinking 1 m a, the minimum output voltage = 25 1 ma = 25 mv ( see figure 26) . 8 initial accuracy presolder ref low is 750 v; output voltage includes the effects of preconditioning drift. see the solder heat reflow section. 9 reference is trimmed and tested at two temperatures and is characterized from ? 40c to +105c . reference temperature coefficient is calculated as per the box method. see the terminology section for more in formation. 10 interface inactive. all dacs active. dac outputs unloaded. 11 all dacs powered down. ac characteristics v dd = 2.7 v to 5.5 v; v ref = 2. 5 v; 1.8 v v logic 5.5 v; r l = 2 k?; c l = 200 pf ; all specifications t min to t max , unless otherwise noted . table 3. parameter 1 , 2 min typ max unit test conditions/comments 3 output voltage settling time 5 7 s ? to ? scale settling to 1 lsb slew rate 0.8 v/s digital -to - analog glitch impulse 0.5 nv - sec 1 lsb change around major carry transition digital feedthrough 0.13 nv - sec digital crosstalk 0.1 nv - sec analog crosstalk 0.2 nv - sec dac -to - dac crosstalk 0.3 nv -s ec total harmonic distortion 4 ?80 db at t a , bw = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density 300 nv/ hz dac code = midscale, 10 khz , gain = 2 output noise 6 v p -p 0.1 hz to 10 hz 1 guaranteed by design and characterization; not production tested. 2 see the terminology s ection. 3 temperature range is ?40c to +105c; typical at 25c. 4 digitally generated sine wave at 1 khz.
data sheet AD5316R rev. a | page 5 of 24 timing characteristi cs v dd = 2. 7 v to 5.5 v; 1.8 v v logic 5.5 v; all specifications t min to t max , unless otherwise noted. table 4. parameter 1 , 2 min max unit description t 1 2.5 s scl cycle time t 2 0.6 s t high , scl high time t 3 1.3 s t low , scl low time t 4 0.6 s t hd,sta , start/repeated start hold time t 5 100 ns t su,dat , data setup time t 6 3 0 0.9 s t hd,dat , data hold time t 7 0.6 s t su,sta , repeated start setup time t 8 0.6 s t su,sto , stop condition setup time t 9 1.3 s t buf , bus free time between a stop condition and a start condition t 10 4 0 300 ns t r , rise time of scl and sda when receiving t 11 4 , 5 20 + 0.1c b 300 ns t f , fall time of scl and sda when transmitting/ receiving t 12 20 ns ldac pulse width t 13 400 ns scl rising edge to ldac rising edge t sp 6 0 50 ns pulse width of suppressed spike c b 5 400 pf capacitive load for each bus line 1 see figure 2 . 2 guaranteed by design and characterization; not production tested. 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min o f the scl signa l) to bridge the undefined region of the scl falling edge. 4 t r and t f are measured from 0.3 v dd to 0.7 v dd . 5 c b is the total capacitance of one bus line in pf . 6 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns. timing diagram figure 2 . 2 - wire serial interface timing diagram scl sda t 1 t 3 ldac 1 ldac 2 start condition repeated start condition stop condition notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 t 6 t 5 t 7 t 8 t 2 t 13 t 4 t 11 t 10 t 12 t 12 t 9 10819-002
AD5316R data sheet rev. a | page 6 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v v logic to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd 1 ?0.3 v to v logic + 0.3 v sda and scl to gnd ?0.3 v to +7 v operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 125c reflow soldering peak temperature, pb free (j - std -020) 260c esd human body model (hbm) 3.5 kv field - induced charged device model ( ficdm ) 1.5 kv 1 excluding sda and scl. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in dicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. this value was measured using a jedec standard 4 - layer board with zero airflow . for the lfcsp package, the exposed pad must be tied to gnd. table 6 . thermal resistance package type ja unit 16 - lead lfcsp 70 c/w 16- lead tssop 112.6 c/w esd caution
data sheet AD5316R rev. a | page 7 of 24 pin configuration s and function descrip tions figure 3 . 16 - lead lfcsp pin configuration figure 4 . 16 - lead tssop pin configuration table 7 . pin function descriptions pin no. mnemonic description lfcsp tssop 1 3 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. 2 4 gnd ground reference point for all circuitry on the part. 3 5 v dd power supply input. the part can be operated from 2.7 v to 5.5 v . the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 6 v out c analog output voltage from dac c. the output amplifier has rail -to - rail operation. 5 7 v out d analog output voltage from dac d. the output amplifier has rail - to - rail operation. 6 8 sd a serial data input. this pin is used in conjunction with the scl line to clock data into or out of the 24- bit input shift register. sda is a bidirectional, open - drain data line that should be pulled to the supply with an external pull - up resistor. 7 9 ldac ldac can be operated in two modes, asynchronous update mode and synchronous update mode . pulsing this pin low allows any or all dac registers to be updated if the input registers have new data ; a ll dac outputs are simultaneously update d . this pin can also be tied permanently low. 8 10 gain gain select pin. when this pin is tied to gnd, all four dac outputs have a span of 0 v to v ref . when this pin is tied to v dd , all four dac outputs have a span of 0 v to 2 v ref . 9 11 v logic digital power supply. voltage ranges from 1.8 v to 5.5 v. 10 12 a0 address input. sets the first lsb of the 7 - bit slave address. 11 13 scl serial c lock line. this pin is used in conjunction with the sda line to clock data into or out of the 24- bit input shift register. 12 14 a1 address input. sets the second lsb of the 7 - bit slave address. 13 15 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is activated (low) , the input register and the dac register are updated with zero scale or midscale, depending on the state of the rstsel pin. when reset i s low, all ldac pulses are ignored. 14 16 rstsel power - on reset pin. when this pin is tied to gnd, all four dacs are power ed up to zero scale. when this pin is tied to v dd , all four dacs are power ed up to midscale. 15 1 v ref reference voltage. the AD5316R has an internal reference . when the internal reference is used , v ref is the reference output pin. when an external reference is used , v ref is the reference input pin. by default , the internal reference is used, and this pin is a reference output. 16 2 v out b analog output voltage from dac b. the output amplifier has rail -to - rail operation. 17 n/a epad exposed pad . the exposed pad must be tied to gnd. 12 11 10 1 3 4 a1 scl a0 9 v logic v out a v dd 2 gnd v out c 6 sda 5 v out d 7 ldac 8 gain 16 v out b 15 v ref 14 rstsel 13 reset AD5316R notes 1. the exposed pad must be tied to gnd. top view (not to scale) 10819-006 1 2 3 4 5 6 7 8 v out b v out a gnd v out d v out c v dd v ref sda 16 15 14 13 12 11 10 9 reset a1 scl gain ldac v logic a0 rstsel top view (not to scale) AD5316R 10819-007
AD5316R data sheet rev. a | page 8 of 24 typical performance characteristi cs figure 5 . internal reference voltage vs. temperature figure 6 . refer ence output temperature drift histogram figure 7 . reference long - term stability ( drift ) figure 8 . internal reference noise spectral density vs. frequency figure 9 . internal reference noise , 0.1 hz to 10 hz figure 10 . internal reference voltage vs. load current ?40 ?20 0 20 40 60 80 100 120 v ref (v) temperature (c) device 1 device 2 device 3 device 4 device 5 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 v dd = 5v 10819-212 90 0 10 20 30 40 50 60 70 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 number of units temperature drift (ppm/c) v dd = 5v 10819-250 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 0 hour 168 hours 500 hours 1000 hours v dd = 5.5v 10819-251 1600 0 200 400 600 800 1000 1200 1400 10 100 1k 10k 100k 1m nsd (nv/ hz) frequency (hz) v dd = 5v t a = 25c 10819- 11 1 ch1 2v m1.0s 1 v dd = 5v t a = 25c 10819-112 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 ?0.005 ?0.003 ?0.001 0.001 0.003 0.005 v ref (v) i load (a) v dd = 5v t a = 25c 10819- 1 13
data sheet AD5316R rev. a | page 9 of 24 figure 11 . internal reference voltage vs. supply voltage figure 12 . inl figure 13 . dnl figure 14 . inl error and dnl error vs. temperature figure 15 . inl error and dnl error vs. v ref figure 16 . inl error and dnl error vs. supply voltage 2.5002 2.5000 2.4998 2.4996 2.4994 2.4992 2.4990 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v ref (v) supply voltage (v) t a = 25c 10819- 1 17 device 1 device 3 device 2 10819-118 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0 156 312 468 624 780 936 inl (lsb) code v dd = 5v t a = 25c internal reference = 2.5v dnl (lsb) code 10819- 1 19 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 code 0 156 312 468 624 780 936 v dd = 5v t a = 25c internal reference = 2.5v 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 110 60 10 error (lsb) temperature (c) inl dnl v dd = 5v t a = 25c internal reference = 2.5v 10819-124 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 error (lsb) v ref (v) inl dnl v dd = 5v t a = 25c 10819-125 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 2.7 5.2 4.7 4.2 3.7 3.2 error (lsb) supply voltage (v) inl dnl v dd = 5v t a = 25c internal reference = 2.5v 10819-126
AD5316R data sheet rev. a | page 10 of 24 figure 17 . gain error and full - scale error vs. temperature figure 18 . zero - code error and offset error vs. temperature figure 19 . gain error and full - scale error vs. supply voltage figure 20 . zero - code error and offset error vs. supply voltage figure 21 . tue v s . temperature figure 22 . tue v s . supply voltage , gain = 1 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temperature (c) gain error full-scale error v dd = 5v t a = 25c internal reference = 2.5v 10819-127 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 ?20 0 20 40 60 80 100 120 error (mv) temperature (c) offset error zero-code error v dd = 5v t a = 25c internal reference = 2.5v 10819-128 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 2.7 5.2 4.7 4.2 3.7 3.2 error (% of fsr) supply voltage (v) gain error full-scale error v dd = 5v t a = 25c internal reference = 2.5v 10819-129 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 2.7 5.2 4.7 4.2 3.7 3.2 error (mv) supply voltage (v) zero-code error offset error v dd = 5v t a = 25c internal reference = 2.5v 10819-130 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?40 ?20 0 20 40 60 80 100 120 total unadjusted error (% of fsr) temperature (c) v dd = 5v t a = 25c internal reference = 2.5v 10819-131 0.10 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 2.7 5.2 4.7 4.2 3.7 3.2 total unadjusted error (% of fsr) supply voltage (v) v dd = 5v t a = 25c internal reference = 2.5v 10819-132
data sheet AD5316R rev. a | page 11 of 24 figure 23 . tue v s . code figure 24 . i dd histogram with external reference, 5 v figure 25 . i dd histogram with internal reference, v ref = 2.5 v , gain = 2 figure 26 . headroom/footroom vs. load current figure 27 . source and sink capability at 5 v figure 28 . source and sink capability at 3 v 10819-133 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 ?0.06 ?0.07 ?0.08 ?0.09 ?0.10 0 156 312 468 624 780 936 1023 total unadjusted error (% of fsr) code v dd = 5v t a = 25c internal reference = 2.5v 25 20 15 10 5 0 540 560 580 600 620 640 hits i dd (ma) v dd = 5v t a = 25c external reference = 2.5v 10819-135 30 25 20 15 10 5 0 1000 1020 1040 1060 1080 1100 1120 1140 hits i dd full scale (ma) v dd = 5v t a = 25c internal reference = 2.5v 10819-136 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 5 10 15 20 25 30 v out (v) load current (ma) sourcing, 2.7v sourcing, 5v sinking, 2.7v sinking, 5v 10819-200 7 ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x8000 0xc000 0x0000 v dd = 5v t a = 25c internal reference = 2.5v gain = 2 10819-138 5 ?2 ?1 0 1 2 3 4 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x8000 0xc000 0x0000 v dd = 3v t a = 25c external reference = 2.5v gain = 1 10819-139
AD5316R data sheet rev. a | page 12 of 24 figure 29 . supply current vs. temperature figure 30 . settling time figure 31 . power - on reset to 0 v figure 32 . exiting power - down to midscale figure 33 . digital - to - analog glitch impulse figure 34 . analog crosstalk, v out a 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?40 110 60 10 current (ma) temperature (c) full-scale zero code external reference, full-scale 10819-140 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 10 320 160 40 80 20 v out (v) time (s) v out a v out b v out c v out d v dd = 5v t a = 25c internal reference = 2.5v ? to ? scale 10819-141 ?0.01 0 0.06 0.01 0.02 0.03 0.04 0.05 ?1 0 6 1 2 3 4 5 ?10 15 10 0 5 ?5 v out (v) v dd (v) time (s) v out d v dd v out a v out b v out c t a = 25c internal reference = 2.5v 10819-142 0 1 3 2 ?5 10 0 5 v out (v) time (s) v out d v out a v out b v out c v dd = 5v t a = 25c internal reference = 2.5v gain = 1 gain = 2 10819-143 2.4988 2.5008 2.5003 2.4998 2.4993 0 12 8 10 4 6 2 v out (v) time (s) channel b t a = 25c v dd = 5.25v internal reference = 2.5v code = 0x7fff to 0x8000 energy = 0.227206nv-sec 10819-144 ?0.002 ?0.001 0 0.001 0.002 0.003 0 25 20 10 15 5 v out ac-coupled (v) time (s) 10819-145 v out b v out c v out d
data sheet AD5316R rev. a | page 13 of 24 figure 35 . 0.1 hz to 10 hz output noise plot, 2.5 v external reference figure 36 . 0.1 hz to 10 hz output noise plot, 2.5 v internal reference figure 37 . noise spectral density figure 38 . total harmonic distortion at 1 k hz figure 39 . settling time vs. capacitive load ch1 10v m1.0s a ch1 802mv 1 t v dd = 5v t a = 25c external reference = 2.5v 10819-146 ch1 10v m1.0s a ch1 802mv 1 t v dd = 5v t a = 25c internal reference = 2.5v 10819-147 0 200 400 600 800 1000 1200 1400 1600 10 1m 100k 1k 10k 100 nsd (nv/ hz) frequency (hz) full-scale midscale zero-scale v dd = 5v t a = 25c internal reference = 2.5v 10819-148 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 20000 16000 8000 12000 4000 2000 18000 10000 14000 6000 thd (dbv) frequency (hz) v dd = 5v t a = 25c internal reference = 2.5v 10819-149 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 1.590 1.630 1.620 1.600 1.610 1.625 1.605 1.615 1.595 v out (v) time (ms) 0nf 0.1nf 0.22nf 4.7nf 10nf v dd = 5v t a = 25c internal reference = 2.5v 10819-150
AD5316R data sheet rev. a | page 14 of 24 terminology relative accuracy or integral nonlinearity (inl) r elative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. figure 12 shows a typical inl vs. code plot . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. t he AD5316R is guaranteed monotonic by design. figure 13 shows a typical dnl vs. code plot. zero - code error zero - code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the AD5316R because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero - code error is ex pressed in mv. figure 18 shows a plot of zero - code error vs. temperature. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed as a percent age of the full - scale range (% of fsr) . figure 17 shows a plot of f ull - scale error vs. temperature. gain error gain error is a measurement of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed in % of fsr. gain temperature coeffic ient gain temperature coefficient is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measurement of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. it can be negative or p ositive. offset error drift offset error drift is a measurement of the change in offset error with change s in tempera ture. it is expressed in v/c. dc power supply rejection ratio (psrr) dc psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for mid scale output of the dac. it is measured in mv/v . v ref is held at 2 .5 v, a n d v dd is varied by 10%. output voltage settling time th e output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input ch ange . digita l -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s ec , and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) (see figure 33 ). digital feedthrough digital feedthrough is a measure ment of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s ec and measured with a full - scale code change on the data bus, that is, from all 0 s to all 1s and vice versa. noise spectral density (nsd) noise spectral density is a measurement of the internally gener - ated random noise. random noise is characterized as a spectral density (nv/hz) and is measured by loading the dac to mid - scale and mea suring noise at the output. it is measured in nv/hz. figure 37 shows a plot of noise spectral density. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load cu rrent change is a measurement of the impact that a change in load current on one dac has on another dac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv - s ec . analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac in response to a change in the output of another dac. to measure analog crosstalk, load one of the input registers with a full - scale code change (all 0s to all 1s and vice versa) , and then execute a software ldac and monitor the output of the dac whose digital code w as not changed. the area of the glitch is expressed in nv - s ec .
data sheet AD5316R rev. a | page 15 of 24 dac -to - dac crosstalk dac - to - dac crosstalk is the glitch impulse transferred to the output of one dac in response to a digital code change and subsequent analog output change of another dac . it is measured by loading one channel with a full - scale code change (all 0s to all 1s and vice versa) using the write to and update commands while monitoring the output of another channel that is at mid - scale. the energy of the glitch is expressed in nv - s ec . total harmonic distortion (thd) thd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac ; thd is a measurement of the harmonics present on the dac output. it is me asured in db. voltage reference temperature coefficient ( tc ) voltage reference tc is a measurement of the change in the reference output voltage with a change in temperature. the reference tc is calculated using the box method, which defines the tc as t he maximum change in the refere nce output over a given tempera ture range expressed in ppm/c , as follow s: 6 10 ? ? ? ? ? ? ? ? ? = temprange v v v tc refnom refmin refmax where: v refmax is the maximum reference output measured over the total temperature range. v refmin is the minimum reference outp ut measured over the total temperature range. v refnom is the nominal reference output voltage, 2.5 v. temprange is the specified temperature range of ? 40c to +10 5c.
AD5316R data sheet rev. a | page 16 of 24 theory of operation digital - to- analog converter t he AD5316R is a quad , 10 - bit, serial input, voltage output dac with an internal reference. the part operate s from supply voltages of 2.7 v to 5.5 v. data is written to the AD5316R i n a 2 4 - bit word format via a 2 - wire serial interface. th e AD5316R incorporate s a power - on reset circuit to ensure that the dac output powers up to a known output state. the device also ha s a software power - down mode that reduces the typical current consumption to 1 a . transfer function the internal reference is on by default. because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n ref out d gain v v 2 where: v ref is the value of the external reference. gain is the gain of the output amplifier and is set to 1 by default. th e gain can be set to 1 or 2 using the gain select pin. when the gain pin is tied to gnd, all four dac outputs have a span of 0 v to v ref . when this pin is tied to v dd , all four dac outputs have a span of 0 v to 2 v ref . d is the decimal equivalent of the binary code that is loaded to the dac register (0 to 1023). n is the dac resolution (10 bits) . dac architecture the dac architecture consists of a string dac followed by an output amplifier. figure 40 shows a block diagram of the dac architecture. figure 40 . single dac channel architecture block diagram the resistor string structure is shown in figure 41. each resistor in the string has a v alue r. the code loaded to the dac register determines the node on the string from which the voltage is tapped off and fed into the output ampl ifier. the voltage is tapped off by closing one of the switches that connect the string to the amplifier. because the AD5316R is a string of resistors, it is guaranteed monotonic. figure 41 . resistor string structure internal reference the AD5316R on - chip reference is on at power - up but can be disabled via a write to a control register. for more information, s ee the internal reference setup section. the 2.5 v, 2 ppm/c internal reference provides a full - scale output of 2.5 v or 5 v , depending on the state of the gain pin. the internal reference is available at the v ref pin. this buffe r ed reference is capable of driving external loads of up to 10 ma . output amplifiers the output buffer amplifier can generate rail - to - rail voltages on its output for an output range of 0 v to v dd . the actual range depends on the value of v ref , the gain pin, the offset error , and the gain error. the gain pin selects the gain of the output . ? when this pin is tied to gnd , all four output s have a gain of 1 , and the output range is from 0 v to v ref . ? when this pin is tied to v dd , all four output s have a gain of 2 , and the output range is from 0 v to 2 v ref . the output amplifiers are capable of driving a load of 1 k? in parallel with 2 n f to gnd. the slew rate is 0.8 v/s with a ? to ? scale settling time of 5 s. input register 2.5v ref dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 10819-052 r r r r r to output amplifier v ref 10819-053
data sheet AD5316R rev. a | page 17 of 24 serial interface t he AD5316R has a 2 - wire , i 2 c- compatible serial interface ( see the i 2 c - bus specification , version 2.1, january 2000, available from philips semiconductor) . see figure 2 for a timing diagram of a typi cal write sequence. the AD5316R can be connected to an i 2 c bu s as a slave device, under the control of a master device . the AD5316R support s sta ndard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 10 - bit address - ing or general call addressing. input shift register the input shift register of the AD5316R is 2 4 bits wide. data is loaded into the device , msb first , as a 24 - bit word under the control of the serial clock input, scl. the input shift register consists of an 8 - bit command byte and a 16 - bit data - word (see figure 42 ). the first eight msbs make up the command byte . ? the first four bits of the command byte are the command bits (c3, c2, c1, and c0), which control the mode of operation of the device ( see table 8 ) . ? the last four bits of the command byte are the address bits ( dac d , dac c , dac b , and dac a ) , which select the dac that is operated on by the command (s ee table 9 ). table 8 . command definitions co mmand bits c3 c2 c1 c0 command 0 0 0 0 no operation 0 0 0 1 write to input register n ( d ependent on ldac ) 0 0 1 0 update dac register n with contents of input register n 0 0 1 1 wr ite to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software r eset (power - on reset) 0 1 1 1 internal r eference setup register 1 x 1 x 1 x 1 reserved 1 x = dont care. table 9 . address bits and selected dacs address bits selected dac channel s 1 dac d dac c dac b dac a 0 0 0 1 dac a 0 0 1 0 dac b 0 0 1 1 dac a and dac b 0 1 0 0 dac c 0 1 0 1 dac a and dac c 0 1 1 0 dac b and dac c 0 1 1 1 dac a, dac b, and dac c 1 0 0 0 dac d 1 0 0 1 dac a and dac d 1 1 1 1 all dacs 1 any combination of dac channels can be selected using the address bits. the 8 - bit command byte is followed by two data bytes, which con - tain the data - word. the data - word comprises the 10 - bit input code, followed by six dont care bits (see figure 42 ). the data bits are transferred to the input register on the 24 falling edge s of scl. commands can be executed on one dac channel, any two or three dac channels, or on all four dac channels , depending on the address bits selected (see table 9 ) . write and update com mands for more information about the ldac function, see the load dac (hardware ldac pin) section. write to input register n (dependent on ldac ) command 0001 allows the user to write to each dac s dedicated input register individually. when ldac is low, the input register is transparent (if not controlled by the ldac mask register). update dac register n with contents of input register n command 0010 loads the dac registers/outputs with the contents of the input registers selected by the address bits (see table 9 ) and update s the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 allow s the user to write to the dac registers and update the dac outputs directly, independent of the state of the ldac pin. figure 42 . input shift register content s db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 dac d dac c dac b dac a d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x command dac address dac data dac data command byte data high byte data low byte 10819-300
AD5316R data sheet rev. a | page 18 of 24 i 2 c slave address the AD5316R has a 7 - bit i 2 c slave address. the five msbs are 00011 and the two lsbs (a1 and a0) are set by the state of the a 1 and a 0 address pin s . the ability to make hardwired changes to a 1 and a 0 allows the user to incorporate up to four AD5316R devices on one bus (see tabl e 10 ). table 10 . device address selection a 1 pin connection a 0 pin connection a 1 bit a 0 bit gnd gnd 0 0 gnd v logic 0 1 v logic gnd 1 0 v logic v logic 1 1 serial operation the 2 - wire i 2 c serial bu s protocol operates as follows: 1. the master initiates a data transfer by establishing a start condition when a high - to - low transition on the sda line occurs while scl is high. the following byte is the address byte, which consi sts of the 7 - bit slave address. 2. the slave device with the transmitted address responds by pulling sda low during the 9 th clock pulse (this is called the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its i nput shift register. 3. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). transitions on the sda line must occur during the low period of scl; sda must remain stable during the high period of scl. 4. after all data bits are read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the 9 th clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse and then high again during the 10 th clock pulse to establish a stop condition. write operation when writing to the AD5316R , the user must begin with a start command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the AD5316R require s two bytes of data for the dac and a command byte that controls various dac functions. three bytes of data must , therefore , be written to the dac with the command byte followed by the most signifi cant data byte and the least significant data byte, as shown in figure 43 . all these data bytes are acknowledged by the AD5316R . a stop condition follows. figure 43 . i 2 c write operation frame 2 command byte frame 1 slave address 1 9 9 1 scl start by master ack by AD5316R ack by AD5316R sda r/w db23 a0 a1 1 0 0 0 1 db22 db21 db20 db19 db18 db17 db16 1 9 9 1 ack by AD5316R ack by AD5316R frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 10819-303
data sheet AD5316R rev. a | page 19 of 24 r ead o peration when reading data back from the AD5316R , the user must begin with a start command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. th e address byte must be followed by the command byte , which determines both the read command that is to follow and the pointer address to read from ; the command byte is also acknowledged by the dac. the user configures the channel to read back the contents o f one or more dac registers and sets the readback command to active using the command byte. following this, the master establishes a repeated start condition , and the address is resent with r/ w = 1. this byte is acknowledged by the dac , i ndicating that it is prepared to transmit data. two bytes of data are then read fro m the dac, as shown in figure 44 . a nack condition from the master , followed by a stop condition , completes the read sequence. i f more than one dac is selected , channel a is read back by default . m ultiple dac readback seque nce when reading data back from multiple AD5316R dac s , the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. th e address byte must be followed by the command byte, which is also acknowledged by the dac. the user selects the first channel to read back using the command byte. following this, the master establishes a repeated start condition, and the address is resent with r/ w = 1. this byte is acknowledged by the dac , indicating that it is prepared to transmit data. the first two bytes of data are then r ead from dac input register n ( select ed using the command byte ) , most significant byte first , as shown in figure 44 . the next two bytes read back are the contents of dac input register n + 1 , and the next bytes read back are the contents of dac input register n + 2. data is read from the dac input registers in this auto - increment ed fashion until a nack followed by a stop condition follows. if the contents of dac input register d are read out , the next two bytes of data that are read are the contents of dac input register a. figure 44 . i 2 c read operation frame 2 command byte frame 1 slave address 1 1 0 0 0 1 a1 a0 r/w db23 db22 db21 db20 db19 db18 db17 db16 9 9 1 start by master ack by AD5316R ack by AD5316R scl scl sda 1 9 9 1 1 9 9 1 ack by AD5316R repeated start by master ack by master frame 4 most significant data byte n frame 3 slave address ack by master nack by master stop by master frame 6 most significant data byte n + 1 frame 5 least significant data byte n 1 0 0 0 1 a1 a0 r/w db15 db14 db13 db12 db11 db10 db9 db8 sda scl (continued) sda (continued) db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 db10 db9 db8 10819-304
AD5316R data sheet rev. a | page 20 of 24 power - down operation command 0100 is designated for the power - down function . the AD5316R provides three separate power - down modes (see table 11 ). these power - down modes ar e software program - mable by setting bit db7 to bit db0 in the inpu t shift register (see table 12) . two bits are associated with each dac channel. table 11 shows how the state of th e se two bits corresponds to the mode of operation of the device. table 11 . modes of operation operating mode pdx1 pdx0 normal operation 0 0 power - down modes 1 k to gnd 0 1 100 k to gnd 1 0 three - state 1 1 any or all dacs (dac a to dac d ) can be powered down to the selected mode by setting th e corresponding bits in the input shift register . see table 12 for the contents of the input s hift register during the power - down/power - up operation. when both bit pd x 1 and bit pd x 0 (where x is the dac selected) in the input shift register are set to 0, the part work s normally with its normal power consumption of 1.1 ma at 5 v . when bit pdx1, bit pdx0, or both bit pdx1 and bit pdx0 are set to 1, the part is in power - down mode. in power - down mode, the supply current falls to 4 a at 5 v. in power - down mode, the output stage is internally switched from the output of the amplifier to a resistor network of known values. in this way, the output impedance of the part is known wh en the part is in power - down mode. table 11 lists the three power - down options . the output is connected internally to gnd through either a 1 k? or a 100 k? resistor, or it is left open - circuited (three - state). the output stage is illustrated in figure 45. figure 45 . output stage during power - down the bias generator, output amplifier, resistor stri ng, and other associated linear circuitry are shut down when power - down mode is activated. however, the contents of the dac register s are unaffected in power - down mode, and t he dac register s can be updated while the device is in power - down mode . the time r equired to exit power - down is typically 2 .5 s for v dd = 5 v . to reduce the current consumption further , the on - chip reference can be powered off (s ee the internal reference setup section ) . load dac (hardware ldac pin) the AD5316R dac has double buffered interfaces consisting of two banks of registers: inp ut registers and dac registers. the user can write to any combination of the input registers (see table 9 ). updates to the dac registers are controlled by the ldac pin. figure 46 . simplified diagram of input loading circuitry for a single dac table 12 . 24 - bit input shift register contents for power - down/power - up operation 1 db23 ( m sb) db22 db21 db20 db19 to db16 db15 to db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) 0 1 0 0 x x pdd1 pdd0 pdc1 pdc0 pdb1 pdb0 pda1 pda0 command bits (c3 to c0) address bits (d ont care ) d ont care power -d own s elect , dac d power -d own s elect , dac c power -d own s elect , dac b power -d own s elect , dac a 1 x = dont care. resistor network v out x dac power-down circuitry amplifier 10819-058 sda scl v out x dac register input shift register output amplifier ldac v ref input register 10-bit dac 10819-059
data sheet AD5316R rev. a | page 21 of 24 instantaneous dac updating ( ldac held low) for instantaneous updating of the dacs, ldac is held low while data is clocked into the input register using command 0001. both the addressed input register and the dac register are updated on the 24 th clock, and the output begins to change (see table 14). deferred dac updating ( ldac pulsed low) for deferred updating of the dacs, ldac is held high while data is clocked into the input register using command 0001. all dac outputs are asynchronously updated by pulling ldac low after the 24 th clock. the update occurs on the falling edge of ldac . ldac mask register command 0101 is reserved for the software ldac function. when this command is executed, the address bits are ignored. when writing to the dac using command 0101, the 4-bit ldac mask register (db3 to db0) is loaded. bit db3 of the ldac mask register corresponds to dac d; bit db2 corresponds to dac c; bit db1 corresponds to dac b; and bit db0 corresponds to dac a. the default value of these bits is 0; that is, the ldac pin works normally. setting any of these bits to 1 forces the selected dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin. this flexibility is useful in appli- cations where the user wishes to select which channels respond to the ldac pin. the ldac mask register allows the user extra flexibility and control over the hardware ldac pin (see table 13). setting the ldac bit (db3 to db0) to 0 for a dac channel allows the hard- ware ldac pin to control the updating of that channel. table 13. ldac overwrite definition load ldac register ldac bit (db3 to db0) ldac pin ldac operation 0 1 or 0 determined by the ldac pin. 1 x 1 dac channels are updated. (dac channels see ldac pin as 1.) 1 x = dont care. hardware reset pin ( reset ) reset is an active low reset that allows the outputs to be cleared to either zero scale or midscale. the clear code value is user select- able via the reset select pin (rstsel). it is necessary to keep reset low for a minimum of 30 ns to complete the operation. when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. the outputs cannot be updated with a new value while the reset pin is low. there is also a software executable reset function that resets the dac to the power-on reset code. command 0110 is designated for this software reset function (see table 8). any events on ldac or reset during power-on reset are ignored. reset select pin (rstsel) the AD5316R contains a power-on reset circuit that controls the output voltage during power-up. when the rstsel pin is tied to gnd, the outputs power up to zero scale (note that this is outside the linear region of the dac). when the rstsel pin is tied to v dd , the outputs power up to midscale. the outputs remain powered up at the level set by the rstsel pin until a valid write sequence is made to the dac. table 14. write commands and ldac pin truth table 1 command description hardware ldac pin state input register contents dac register contents 0001 write to input register n (dependent on ldac ) v logic data update no change (no update) gnd 2 data update data update 0010 update dac register n with contents of input register n v logic no change updated with input register contents gnd no change updated with input register contents 0011 write to and update dac channel n v logic data update data update gnd data update data update 1 a high to low transition on the hardware ldac pin always updates the contents of the dac register with the contents of the input register on channels that are not masked (blocked) by the ldac mask register. 2 when the ldac pin is permanently tied low, the ldac mask bits are ignored.
AD5316R data sheet rev. a | page 22 of 24 i nternal reference se tup b y default , t he internal reference is on at power - up. to re duc e the supply current, th e on - chip reference can be turned off . command 0111 is reserved for setting up the internal reference. to turn off the internal reference, set the software programmable bit, db0, in the input shift register using command 0111, as shown in table 16. table 15 shows how the state of the db0 bit corresponds to the mode of operation . table 15. internal reference setup register internal reference setup register ( bit db0) action 0 reference on (default) 1 reference off solder heat reflow as with all ic reference voltage circuits, the reference value experiences a shift induced by the soldering process. analog devices, inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. the output volt age specification in table 2 includes the effect of this reliability test. figure 47 shows the effect of solder heat reflow (shr) as measured through the r eliability test (precondition). figure 47 . shr reference voltage shift long - term temperature dri ft figure 48 shows the change in the v ref value after 1000 h ou rs in life test at 150c. figure 48 . reference drift to 1000 hours thermal hysteresis thermal h ysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, then to hot , and then back to ambient. thermal h ysteresis data is shown in figure 49 . it is measured by sweeping the temperature from ambient to ?40c, then to + 105c, and then back to ambient. the v ref delta is then measured between the two ambient measurements (shown in blu e in figure 49 ). the same temperature sweep and measurements were immediately repeated , and the results are shown in red in figure 49. figure 49 . thermal hysteresis table 16 . 24 - bit input shift register contents for internal reference setup command 1 db23 (msb) db22 db21 db20 db19 to d b 1 6 db 1 5 to db1 db0 (lsb) 0 1 1 1 x x 1 or 0 command bits (c3 to c0) address bits (dont care) dont care reference setup register 1 x = dont care. 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) postsolder heat reflow presolder heat reflow 10819-060 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 0 hour 168 hours 500 hours 1000 hours 10819-061 9 8 7 6 5 4 3 2 1 0 50 0 ?50 ?100 ?150 ?200 hits distortion (ppm) first temperature sweep subsequent temperature sweeps 10819-062
data sheet AD5316R rev. a | page 23 of 24 applications informa tion microprocessor inter facing microprocessor interfacing to the AD5316R is via a serial bus that uses a standard protocol that is compatible with dsp proces sors and microcontrollers. the communications channel req uires a 2 - wire interfa ce consisting of a clock signal and a da ta signal. ad5 316r to adsp- bf531 interface the i 2 c interface of the AD5316R is designed for easy connec - tion to industry - standard dsps and microcontrollers. figure 50 shows the AD5316R connect ed to the analog devices blackfin? processor . the blackfin processor has an integrated i 2 c port that can be connected directly to the i 2 c pins of the AD5316R . figure 50 . AD5316R to adsp - bf531 interface layout guidelines in any circuit where accuracy is important, careful consider - ation of the power supply and ground return layout h elps to ensure the rated performance. the pcb on which the AD5316R is mounted should be designed so that the AD5316R lie s on the analog plane. the AD5316R should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply , located as close to the package as possible, ideally right up against the dev ice. the 10 f capacitor i s the tantalum b ead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi) , such as the common ceramic types ; these capacitors provide a low impedance path to ground at high frequencies to handle transient cu rrents d ue to internal logic switching. in systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate e asily. the AD5316R lfcsp model s have an exposed pad beneath the device. connect this pad to the gnd supply for the part. for optimum performance, use special considerations to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, solder the exposed pad on the bottom of the lfcsp package to the corresponding thermal land paddle on the pcb. design thermal vias into the pcb land paddle area to fu rther improve heat dissipa tion. the gnd plane on the device can b e increased (as shown in figure 51 ) to provide a natural heat sinking effect. figure 51 . paddle conne ction to board galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous co mmon - mode voltages that may occur. the analog devices i coupler? products provide voltage isolation in excess of 2 .5 kv. the serial loading struc ture of the AD5316R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 52 shows a 4 - channel isolated interfac e to the AD5316R using the adum1400 . for more information, visit http://www.analog.com/icouplers . figure 52 . isolated interface adsp-bf531 scl gpio1 sda gpio2 ldac pf9 reset pf8 AD5316R 10819-164 AD5316R gnd plane board 10819-166 encode serial clock in controller adum1400 serial data out reset out load dac out decode to scl to sda to reset to ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 10819-167
AD5316R data sheet rev. a | page 24 of 24 outline dimensions figure 53 . 16 - lead lead frame chip scale package [lfcsp _wq ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22 ) dimensions shown in millimeters figure 54 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 resolution temperature range accuracy (inl) reference t empco (ppm/c) package description p ackage option branding AD5316Rbcpz - rl7 10 bits ?40c to +105c 0. 5 lsb 5 (max) 16- lead lfcsp_wq cp -16-22 dj t AD5316Rbruz 10 bits ?40c to +105c 0. 5 lsb 5 (max) 16- lead tssop ru -16 AD5316Rbruz - rl7 10 bits ?40c to +105c 0. 5 lsb 5 (max) 16- lead tssop ru -16 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10819 - 0 - 7/12(a)

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